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Introduction
semiconductor industry. The main factor of producing complex devices at lower cost is lithography. Optical lithography has been reaching the physical limit and therefore leads to the development of alternate techniques. Immersion lithography has recently attracted interest in the research industry. Of other alternatives, many consider extreme ultraviolet lithography and nano-imprint lithography as potential successors to optical lithography. Lastly we also analyze the potential of x-ray lithography and electron beam lithography as possible candidates.
Immersion Lithography
The uniqueness about Immersion Lithography is seen in the replacement of air with ultrapure water as the medium between the lens and the wafer. This pushes the physical limits of NA for the exposure systems beyond NA=1 for air, given the following relation: NA=n sin alpha = d/2f. Ultra pure water is highly suitable as it has a refraction index of 1.47, absorption of <5%>
Extreme Ultraviolet Lithography
EUVL uses light sources with wavelength (13.4nm) 10 times shorter than current wavelengths (139nm). This will make possible fabrication of circuit lines smaller than 0.1 microns in width, extendable to below 30nm. EUVL masks are reflective masks, with a patterned absorber of EUV radiation placed on top of an ML (multilayer thin film with alternating layers of Mo and Si) reflector deposited on a robust and solid substrate, such as a silicon wafer. The key requirement is to make a mask with essentially no defects. The strong absorption of EUV radiation by all materials poses the main problem in developing a satisfactory photoresist for EUV lithography. . The thin layer imaging is already a mature technology, thus resist is no longer a critical issue. Printed lines as small as 50nm in photoresist has already been achieved.
The Virtual National Laboratory (VNL) formed by the three Laboratories - Lawrence Livermore, Lawrence Berkeley, and Sandia/California, has developed and built a prototype extreme ultraviolet lithography (EUVL) system called the engineering test stand (ETS). This ETS has produced test patterns with a line-to-spacing ratio of 1:1 with high fidelity down to line widths of 70 nm using its Set-2-optic. By adjusting the illumination pattern and the exposure dose, the team printed less densely spaced lines with widths down to 39 nm. It is thus able to meet the production requirements set for chips with 1 billion transistors and up in the years 2007 to 2010.
X-ray Lithography
The basic set up of a typical XRL system is by using a synchrotron as an x ray source. Synchrotron-based XRL provides a wide exposure-dose window, which is very important in ULSI fabrication. Insensitivity to dust is another advantage, which will affect the amount of pattern defects. The source is an electromagnetic wave, which is generated when high-energy electrons are accelerated. To minimize x ray absorption, the mask substrate is made of a thin membrane consisting of materials with a low atomic number. The issue pertaining to this method is that here is a need for an overlay accuracy which will meet the requirements of sub -0.1-um ULSI fabrication, while another issue is throughput. By properly choosing of median wavelength, proximity x-ray lithography (PXRL) can be extended to 50nm using relatively large mask/wafer gaps. This can be achieved by increasing the energy of the storage ring, decreasing the incident angle on the beamline mirror, and utilizing a diamond mask substrate. Increasing the median energy to 2.6 to 2.7keV allows printing of smaller features down to 35nm by using a harder spectrum, choosing the appropriate materials for the mask and the resist match the transmission and absorption at this high energies.
Electron beam lithography
Electron beam lithography applies direct writing method to scan electron beam across various material surface covered with resist film to create desired extensive patterns on the substrates. Because of the high energy electron beam (tens to hundred eV), it totally eliminates the diffraction effect; however, it can make damages to the substrate material. The resolution is now limited by aberration of electron optics and scattering effects which is more severe. Through scattering effect correction, it can reach a resolution about 10-20nm. As the pattern generation is carried out through scanning the surface pixel by pixel controlled by computer aided design (CAD), this leads to very slow speed, thus very low throughput. Although this E-beam direct writing does not require a mask which usually costs a lot for specific material, delicate equipment cost and frequent maintains are usually very expensive up to millions of dollars, thus mass production is economically unfavorable. These speed and cost considerations limit its application in mass commercial production for 50 nm feature size although it has a high level resolution. Instead this technique is used to produce high quality mask with good resolution and also widely used in research purpose.
Nano-imprint Lithography (NIL)
NIL creates a resist relief pattern by deforming the resist physical shape with embossing, instead of modifying the resist chemical structure with radiation or creating the pattern by self-assembly. The pattern is then transferred into the material to be etched (a Si wafer for example) using the resist as a mask. The key advantage of this lithographic technique is the ability to pattern sub-25 nm structures over a large area with a high-throughput and low-cost. Unlike conventional lithography methods, imprint lithography itself does not use any energetic beams. Therefore, nano-imprint lithography’s resolution is not limited by the effects of wave diffraction, scattering and interference in a resist, and backscattering from a substrate.
There are two advancements in this technology recently. A new UV based nanoimprint lithography (UV-NIL) has been developed and demonstrated at AMO as attractive alternative to the hot embossing technique. The low pressure (<1bar) style="">Researchers at
Comparison
In choosing the most promising technology that could allow for 50nm feature size and below, we considered the following factors in our decision. They are the cost of the technology, the throughput of the method, the amount of constraints that it is facing at the moment and the possibility of the technology to produce 50nm feature size.
